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The Dynamic Vedic Multiplier Implemented in Fpga for Dsp Applications: High Speed Digital Design Sivaramakrishnan S.
The Dynamic Vedic Multiplier Implemented in Fpga for Dsp Applications: High Speed Digital Design
Sivaramakrishnan S.
Now-a-days an interest in the Vedic system is growing well in technology next to education. Developing a effective algorithim for VLSI from Vedic Mathematical Sutras(Formulae) in calculus, computing, square, Cube etc. Sri Bharati Krsna Tirthaji (1884-1960) has given the complete mathematical calculations in a easiest way ever. But the real beauty of Vedic Mathematics cannot be fully appreciated without used it in a technology Properly. One can then see that it is perhaps the most refined and efficient mathematical system which implemented in the digital signal application. This initiative work should be extended up-to a practical application. Constructive criticisms and suggestions from researchers and student scholars regarding this book are welcome. -B. Divya
| Media | Books Paperback Book (Book with soft cover and glued back) |
| Released | February 26, 2013 |
| ISBN13 | 9783659353598 |
| Publishers | LAP LAMBERT Academic Publishing |
| Pages | 56 |
| Dimensions | 150 × 3 × 226 mm · 102 g |
| Language | German |
See all of Sivaramakrishnan S. ( e.g. Paperback Book )